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VNF9D5F Datasheet(PDF) 40 Page - STMicroelectronics |
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VNF9D5F Datasheet(HTML) 40 Page - STMicroelectronics |
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40 / 108 page  SOCR Channel control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - R/W - R/W - R/W R Address: 0x13h Type: R/W Reset: 0 Description: Channel control register [15:14] - [13] Exit capacitive charging mode on channel 1 (active high). This bit is automatically reset. [12] Exit capacitive charging mode on channel 0 (active high). This bit is automatically reset. [11:10] - [9] SOCR bit controls output state of channel 1 1 – output enabled 0 – output disabled [8] SOCR bit controls output state of channel 0 1 – output enabled 0 – output disabled [7:4] - [3] Capacitive charging mode on channel 1 1 – enabled 0 – disabled This bit is automatically reset. [2] Capacitive charging mode on channel 0 1 – enabled 0 – disabled This bit is automatically reset. [1] Watchdog toggle bit [0] Parity bit VNF9D5F SPI functional description DS13946 - Rev 8 page 40/108 |
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