VNF9D5F datasheet(60/108 Pages) STMICROELECTRONICS

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5.6

Open-load off-state detection

After the channel is completely OFF, if the output voltage VOUT exceeds the open-load detection threshold voltage

VDSH_TH, an open-load OFF-state/Stuck to VCC event is detected.

It is possible to monitor the voltage drop on the PowerMOS per each channel, checking the content of the

corresponding real time bit VDSHSRx in the OUTSRx registers (addresses from 0x20h to 0x21h). When channel

x is in off-state, if VDS is lower than the threshold (VCC - VDSH_TH), the VDSHSRx bit is low, otherwise it is in high

state.

In normal operation, a low value of bit VDSHSRx in off-state must be interpreted as a potential Stuck to VCC

condition. However, setting OLOFFCR bit in the OUTCTRCRx register (addresses from 0x00h to 0x01h), it is

possible to activate an internal pull-up current generator for the corresponding channel x. In this case a low value

of bit VDSHSRx in off-state may indicate either a potential Stuck to VCC or an Open load condition. In the latter

case, when the internal pull-up current generator is disabled the bit VDSHSRx is high.

To avoid false fault indications, it is recommended to perform these checks when the channel is in a permanent

off-state condition.

The pull-up current generators can be activated in normal, fail-safe and pre-standby modes; whilst they are

switched off in standby mode. Either a HW or SW reset (VREG < VPOR respectively FFh command byte) clears all

Figure 30. Open-load OFF-state detection

GADG1004171620PS

SPI register: OLOFFCR

Open-load OFF state control register

VCC

VOUT

VDS

GND

Table 42. VDSHSR state in a permanent off-state condition

Case

VDSHSR state in a permanent off-state condition

With internal pull-up generator

Without internal pull-up generator

Case 1: load connected

"1" / no fault condition

Case 2: no load

"0" / fault

"1" / no fault signal

Case 3: output shorted to VCC

"0" / fault

5.7

Direct input status bits in OUTSRx (DIENSR)

The DIENSR bits read back the logic level of the DIx input assigned through OTP to the specific channel.

5.8

Channel feedback status bit in OUTSRx (CHFBSR)

The CHFBSRx bit provides a logical "OR" combination of PL, OT failure flags related to OUTPUTx. If CHFBSRx

bit is set, the channel OUTPUTx is failing, otherwise, NO failure is present. The bits are refreshed continuously in

ON-state and latched in OFF-sate. In order to clear the bit in OFF-state, a Read&Clear command has to be

performed.

VNF9D5F

Diagnostic

DS13946 - Rev 8

page 60/108

VNF9D5F Datasheet(PDF) 60 Page - STMicroelectronics

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