VNF9D5F datasheet(7/108 Pages) STMICROELECTRONICS

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Table 2. Operating modes

Operating mode

Entering conditions

Leaving conditions

Characteristics

Start:

transition phase

(not operating

mode) where

neither VREG nor

VCC are available.

The device leaves this phase to

enter sleep mode when:

System startup, VCC present

• VREG < VREG_POR_H

• VCC < VUSD

• Outputs: OFF

• SPI: inactive

• Registers: reset values

• Diagnostics: not available

Sleep mode:

in this state, the

device has very low

consumption

(IDDstdby, ISOFF)

• From start phase: as soon as

Vbat > VUSD is applied to VCC pin

• From normal or fail-safe mode

or pre-standby mode or standby

mode: VREG < VREG_POR_L

The device leaves this state to

enter fail

‑safe mode when:

• VREG > VREG_POR_H

• VREG < VREG_POR_H

• Outputs: OFF

• SPI: inactive

• Registers: reset values

• Diagnostics: not available

• Very low supply current from VDD and VCC

Standby mode:

in this state, the

device has low

consumption

From pre-standby mode: As

soon as STDBY_NOT low AND

(CSN high OR VDD < VDD_TH)

AND all I²t counters = 0 AND

tstdby elapsed

The device leaves this state to

enter sleep mode when:

VREG < VREG_POR_L;

The device leaves this state to

enter fail

‑safe mode when:

STDBY_NOT high OR (CSN low

AND VDD > VDD_TH)

• VREG > VREG_POR_H

• Outputs: OFF

• SPI: inactive

• Registers: not readable

• Diagnostics: not available

• Low supply current from VDD and VCC

Fail-safe mode:

(Limp-home)

• From pre-standby mode:

STDBY_NOT = 1 OR (CSN low

AND VDD > VDD_TH)

• From standby mode:

[STDBY_NOT = 1 OR (CSN low

AND VDD > VDD_TH)] AND VREG

> VREG_POR_H

• From normal mode: EN_bit = 0

OR WDTB timeout (tWDTB) OR

SW reset

• From sleep mode:

[STDBY_NOT = 1 OR (CSN low

AND VDD > VDD_TH)],

VREG > VREG_POR_H

• If VREG < VREG_POR_L, the

device enters sleep mode

• If STDBY_NOT = 0 AND (CSN

high OR VDD < VDD_TH) for at

least tprestdby, the device enters

pre-standby mode

• If the SPI sends the following

sequence, the device enters

normal mode:

1st communication frame:

• UNLOCK bit = 1

2nd communication frame:

• EN bit = 1 AND GOSTBY bit = 0

This procedure avoids entering

the normal mode unintentionally.

• VREG > VREG_POR_H

• Outputs: according toDIx, DIOTPx, MCUext

• SPI: active

• Registers: read/write possible, cleared if

entered after SW reset

• Diagnostics: available through SPI, ADC

conversion available only in asynchronous mode

• Reset bit: set to 1 if the last state is Standby

mode or in case the last command is a SW

reset; it is reset to 0 at the first SPI access

• Protections: available. In case of over

temperature or power limitation, the outputs work

in auto-restart.

• Harness protection: available for all channels.

The channels are configured in autorestart mode

if MCUext bit = 1

Normal mode:

the transition to this

device state is

possible ONLY from

fail-safe state.

• If it is in fail-safe AND the SPI

sends the following sequence:

1st communication frame:

• UNLOCK = 1

2nd communication frame:

• GOSTBY = 0 AND EN = 1

This procedure avoids entering

the normal mode unintentionally.

• If VREG < VREG_POR_L, the

device enters the sleep mode

• If the SPI clears the EN bit (EN

bit = 0), the device enters the fail-

safe

• If WDTB is not toggled within the

timeout period tWDTB, the device

enters fail-safe mode

• If the SPI sends a SW reset, the

device enters the fail-safe mode

and all the registers are cleared

• If the SPI sends the following

sequence, the device enters the

pre-standby mode:

• Outputs: according to SPI register settings

and/or DIx

• SPI active

• Diagnostic: available

• Registers: read/write is allowed

• Protections: available. The outputs can be set

to “latch” or “time limited auto-restart”. In “time

limited auto-restart”, the outputs are

automatically switched on after an over

temperature or power limitation event for a

limited cumulated time duration; whilst in “latch”,

the relevant status register must be cleared to

switch them on again.

• Harness protection: available for all channels.

The channels are configured in latch mode;

VNF9D5F

Functional description

DS13946 - Rev 8

page 7/108

VNF9D5F Datasheet(PDF) 7 Page - STMicroelectronics

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