VNF9D5F datasheet(30/108 Pages) STMICROELECTRONICS

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Bit 1

Bit 0

Description

Invalid

In case either the Parity or the CRC check is implemented it is always located at the end of the communication.

The device is equipped with the parity control check.

4.4

Outputs control

Depending on the actual device mode, outputs can be controlled by the SPI register or the direct input DIx.

SPI register SOCR

In normal mode outputs can be turned ON/OFF, applying Bit[n] = 1/0 in the SOCR register.

[n]: is the related channel, n = 0 for the channel 0, and n = 1 for channel 1.

Procedure to turn-ON the outputs in PWM operations

The status of the output drivers is configured via the SPI output control register (SOCR), the direct input enable bit

“DIENCR” in the OUTCFGRx register, the PWM mode control register (PWMFCY) and the channel control

by the SOCR. The PWMFCY bit selects if the outputs operate in PWM mode. Please refer to the following table

for Output Control details in Normal Mode.

Table 31. Output control truth table

DIENCR (OUTCFGRx)

INx

SOCRx

DUTYCR

OUTPUTx

OFF

PWM

OFF

PWM

Note:

•

In normal mode, outputs can be driven by SPI commands or a combination of SPI commands and direct

inputs INx.

•

In fail-safe mode, the outputs are controlled by the direct inputs DIx regardless of SPI commands. It is

possible to apply the PWM through the DIx inputs. The PWM unit is not active in fail-safe mode, it is still

possible to access the relevant registers and to configure them.

To turn on channels, information must enter into the following registers

•

Select the PWM frequency by using the two bits PWMFCYx

•

Select the PHASE information by using the 5 bits CHPHAx

•

Select the switching slope by using the two bits SLOPECRx

•

Select the channels configuration Bulb/LED by using the bit CCR

•

Select the DUTYCYCLE information by using the 10 bits of the OUTCTRCRx registers

•

Select the channel through the dedicated register “SOCR” in the Channel Control register

•

Select the PWM triggering mode by using the single bit PWM_TRIG of the CTRL register

The PWMSYNC bit will reset the internal 12 bits clock counter. This allows to have a known time base and to

synchronize different devices among each other.

The signal on the PWMCLK is divided internally by a factor from 4096 to 512 depending on the PWMFCY register

to generate the base frequency for the output:

•

PWM signal is generated by properly selecting 10 of 12 bits on the clock counter. PWM engine has a virtual

10-bit granularity except when PWM divider is set to 512, in this case only a 9-bit granularity is possible

(LSB of 10bit generated PWM is fixed to zero). Duty cycle step can be modified with the granularity related

to the 9-bit register.

VNF9D5F

SPI functional description

DS13946 - Rev 8

page 30/108

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