VNF9D5F datasheet(65/108 Pages) STMICROELECTRONICS

65 / 108 page

6.5

Registers

For more details refer to the SPI register and diagnostics.

•

Address 010h - Channel Latch OFF Timer Control Register (CHLOFFTCR0)

One 16-bit register (Latch-OFF timer: R/W) is used for the channel behavior configuration and the timer value

setting.

For each channel 4 bits are used. The value is written by MCU from 0x0 to 0xF.

Figure 34. Example of behavior channel configuration

ch1

Dual device

ch1

ch0

Latch-Off timer register access:

•

Write command - store new value, read-back (during write command) old value equal to the timer down-

counting.

–

Any write command will clear the flag in the latch-OFF-flag register and reset the timer.

–

This function will be used by MCU to clear the flag in the latch-OFF-flag register, which is a read only

•

Read command - read currently down-counted timer value. If the channel was latched because of timer

expiration, the channel is kept latched after read command.

•

Channels latch-off status bit - CHLOFFSRx in OUTSRx. Each channel has one CHLOFFSR flag. In case of

latch-OFF of a channel, this flag will be set and readable by MCU. This bit must be cleared to allow the

channel to resume operation through a read/clear operation.

6.6

Digital power management

A new pin (VREG) has been added, to supply the digital part. VDD pin remains in charge for digital I/O and pins

supplying to be compatible with system architecture. A capacitor in series with a resistance may be externally

connected to VREG pin (vs device GND) to sustain digital part power supply in case of fast battery interruption.

The capacitor is charged at a pre-regulated voltage (4.7 V) directly from internal battery reference.

In case VDD regulated voltage is supplied, an external diode may be connected between VDD pin (anode) and

VREG pin (cathode).

VNF9D5F

Programmable blanking window (PBW)

DS13946 - Rev 8

page 65/108

VNF9D5F Datasheet(PDF) 65 Page - STMicroelectronics