TPS54821 datasheet(18/42 Pages) TI2

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VSENSE

COMP

VOUT

Coea

Roea

1300 mA/V

0.6 V

Power Stage

RESR

21 A/V

TPS54821

SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016

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Device Functional Modes (continued)

While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During

normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side

MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side

sourcing current is exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the

next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing

current limit at the start of a cycle.

The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the

low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are

off until the start of the next cycle.

Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than

the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart

after the hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under

severe overcurrent conditions.

7.4.11 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

175°C typically. Once the junction temperature drops below 165°C typically, the internal thermal hiccup timer will

start to count. The device reinitiates the power up sequence after the built-in thermal shutdown hiccup time

(16384 cycles) is over.

7.4.12 Small Signal Model for Loop Response

Figure 25 shows an equivalent model for the device control loop which can be modeled in a circuit simulation

program to check frequency response and transient responses. The error amplifier is a transconductance

amplifier with a gm of 1300

μA/V. The error amplifier can be modeled using an ideal voltage controlled current

source. The resistor Roea (3.07 M

Ω) and capacitor Coea (20.7 pF) model the open loop gain and frequency

response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the

control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of

the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the

overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the

appropriate load step amplitude and step rate in a time domain analysis.

Figure 25. Small Signal Model for Loop Response

7.4.13 Simple Small Signal Model for Peak Current Mode Control

Figure 26 is a simple small signal model that can be used to understand how to design the frequency

compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle

modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is

shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the

change in switch current and the change in COMP pin voltage (node c in Figure 25) is the power stage

transconductance (gmps) which is 21 A/V for the device. The DC gain of the power stage is the product of gmps

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