(

)

-

=

×

×

Vinmin

Vout

Vout

Icirms

Iout

Vinmin

Vinmin

(

)

12

f

×

-

=

×

×

×

Vout

Vinmax

Vout

Icorms

Vinmax L1

sw

<

Voripple

Resr

Iripple

1

1

8

f

>

×

×

Co

Voripple

sw

Iripple

2

f

× D

>

× D

Iout

Co

sw

Vout

23

TPS54821

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SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016

Product Folder Links: TPS54821

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Copyright © 2011–2016, Texas Instruments Incorporated

The desired response to a large change in the load current is the first criteria. The output capacitor needs to

supply the load with current when the regulator can not. This situation would occur if there are desired hold-up

times for the regulator where the output capacitor must hold the output voltage above a certain level for a

specified amount of time after the input power is removed. The regulator is also temporarily not able to supply

sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from

no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change

in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be

sized to supply the extra current to the load until the control loop responds to the load change. The output

capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a

tolerable amount of droop in the output voltage. Equation 22 shows the minimum output capacitance necessary

to accomplish this.

(22)

Where

ΔIout is the change in output current, Fsw is the regulators switching frequency and ΔVout is the

allowable change in the output voltage. For this example, the transient load response is specified as a 7%

change in Vout for a load step of 4 A. For this example,

ΔIout = 4 A and ΔVout = 0.07 x 3.3 = 0.231 V. Using

these numbers gives a minimum capacitance of 72.2

μF. This value does not take the ESR of the output

capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to

ignore in this calculation.

Equation 23 calculates the minimum output capacitance needed to meet the output voltage ripple specification.

Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the

inductor ripple current. In this case, the maximum output voltage ripple is 33mV. Under this requirement,

Equation 23 yields 14.6 µF.

(23)

Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple

specification. Equation 24 indicates the ESR should be less than 17.9 m

Ω. In this case, the ceramic caps’ ESR is

much smaller than 17.9 m

Ω.

(24)

Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this

minimum value. For this example, 2 x 47

μF 10 V X5R ceramic capacitor with 3 mΩ of ESR are used. Capacitors

generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An

output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets

specify the RMS (Root Mean Square) value of the maximum ripple current. Equation 25 can be used to calculate

the RMS ripple current the output capacitor needs to support. For this application, Equation 25 yields 485mA.

(25)

8.2.2.5 Input Capacitor Selection

The TPS54821 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 µF of

effective capacitance on the PVIN input voltage pins and 4.7 µF on the Vin input voltage pin. In some

applications additional bulk capacitance may also be required for the PVIN input. The effective capacitance

includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input

voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the

TPS54821. The input ripple current can be calculated using Equation 26.

(26)