TPS54821 datasheet(25/42 Pages) TI2

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Frequency

100Hz

1.0KHz

10KHz

100KHz

1.0MHz

Phase - Degrees

-60

-40

-20

-0

-180d

-120d

-60d

60d

120d

180d

Gain - dB

-137 deg

-8.281 dB

p ´

Iout m ax

p m od =

Vout

Cout

(

)

(

)

(

)

Voutmin

Ontimemin Fsmax Vinmax

Ioutmin RDS2min

RDS1min

Ioutmin RL

RDS2min

TPS54821

www.ti.com

SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016

Product Folder Links: TPS54821

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Where:

Voutmin = minimum achievable output voltage

Ontimemin = minimum controllable on-time (135 nsec maximum)

Fsmax = maximum switching frequency including tolerance

Vinmax = maximum input voltage

Ioutmin = minimum load current

RDS1min = minimum high side MOSFET on resistance (36-32 m

Ω typical)

RDS2min = minimum low side MOSFET on resistance (19 m

Ω typical)

RL = series resistance of output inductor

(30)

8.2.2.10 Compensation Component Selection

There are several possible methods to design closed loop compensation for dc/dc converters. For the ideal

current mode control, the design equations can be easily simplified. The power stage gain is constant at low

frequencies, and rolls off at –20 dB/decade above the modulator pole frequency. The power stage phase is 0

degrees at low frequencies and starts to fall one decade above the modulator pole frequency reaching a

minimum of –90 degrees one decade above the modulator pole frequency. The modulator pole is a simple pole

shown in Equation 31

(31)

For the TPS54821 most circuits will have relatively high amounts of slope compensation. As more slope

compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase

loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage

transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple

approximations. It is best to use Pspice or TINA-TI to accurately model the power stage gain and phase so that a

reliable compensation circuit can be designed. That is the technique used in this design procedure. Using the

pspice model for the TPS54821, apply the values calculated previously to the output filter components of L1, C7

and C8. Set RLOAD to the appropriate value for the current value to be compensate. For this design, L1 = 3.3 µH.

C7 and C8 use the derated capacitance value of 37.6 µF, and the ESR is set to 3 m

Ω. The RLOAD resistor is 3.3

V/4 A = 0.82

Ω. Now the power stage characteristic can be plotted as shown in Figure 30.

Figure 30. Power Stage Gain and Phase Characteristics

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