×

-

REF

OUT

REF

R7 V

R8 =

V

V

(

)

(

)

( )

m

×

=

Tss ms Iss

A

C6(nF)

Vref V

0.25

f

×

D

=

×

Ioutmax

Vin

Cin

sw

24

TPS54821

SLVSB14B – OCTOBER 2011 – REVISED FEBRUARY 2016

www.ti.com

Product Folder Links: TPS54821

Submit Documentation Feedback

Copyright © 2011–2016, Texas Instruments Incorporated

The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the

capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that

is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors

because they have a high capacitance to volume ratio and are fairly stable over temperature. The output

capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor

decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at

least a 25 V voltage rating is required to support the maximum input voltage. For this example, one 10

μF and

one 4.7 µF 25 V capacitors in parallel have been selected as the VIN and PVIN inputs are tied together so the

TPS54821 may operate from a single supply. The input capacitance value determines the input ripple voltage of

the regulator. The input voltage ripple can be calculated using Equation 27. Using the design example values,

Ioutmax = 8 A, Cin = 14.7

μF, Fsw=480 kHz, yields an input voltage ripple of 417 mV and a RMS input ripple

current of 3.94 A.

(27)

8.2.2.6 Slow Start Capacitor Selection

The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its

nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This

is also used if the output capacitance is very large and would require large amounts of current to quickly charge

the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the

TPS54821 reach the current limit or excessive current draw from the input power supply may cause the input

voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor

value can be calculated using Equation 28. For the example circuit, the soft start time is not too critical since the

output capacitor value is 2 x 47

μF which does not require much current to charge to 3.3 V. The example circuit

has the soft start time set to an arbitrary value of 6 ms which requires a 22nF capacitor. In TPS54821, Iss is

2.3µA and Vref is 0.6V.

(28)

8.2.2.7 Bootstrap Capacitor Selection

A 0.1 µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is

recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10V or

higher voltage rating.

8.2.2.8 Under Voltage Lockout Set Point

The Under Voltage Lock Out (UVLO) can be adjusted using the external voltage divider network of R3 and R4.

R3 is connected between VIN and the EN pin of the TPS54821 and R4 is connected between EN and GND .

The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or

brown outs when the input voltage is falling. For the example design, the supply should turn on and start

switching once the input voltage increases above 6.528V (UVLO start or enable). After the regulator starts

switching, it should continue to do so until the input voltage falls below 6.190 V (UVLO stop or disable).

Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the

stop voltages specified the nearest standard resistor value for R3 is 35.7 k

Ω and for R4 is 8.06 kΩ.

8.2.2.9 Output Voltage Feedback Resistor Selection

The resistor divider network R7 and R8 is used to set the output voltage. For the example design, 10 k

Ω was

selected for R7. Using Equation 29, R8 is calculated as 2.22 k

Ω. The nearest standard 1% resistor is 2.21 kΩ.

(29)

8.2.2.9.1

Minimum Output Voltage

Due to the internal design of the TPS54821, there is a minimum output voltage limit for any given input voltage.

The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output

voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by

Equation 30