F24 datasheet(145/210 Pages) RENESAS

145 / 210 page

RL78/F23, F24

4. ELECTRICAL SPECIFICATIONS (GRADE 4)

R01DS0446EJ0120 Rev.1.20

Page 145 of 207

Dec 31, 2025

4.12 Timing of Entry to Flash Memory Programming Modes

(TA = -40 to +125

°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Time to complete the communication

for the initial setting after the external

reset is released

tSUINIT

POR and LVD reset must be released

before the external reset is released.

100

Time to release the external reset after

the TOOL0 pin is set to the low level

tSU

POR and LVD reset must be released

before the external reset is released.

µs

Time to hold the TOOL0 pin at the low

level after the external reset is released

(excluding the processing time of the

firmware to control the flash memory)

tHD

POR and LVD reset must be released

before the external reset is released.

<1> The low level is input to the TOOL0 pin.

<2> The external reset is released (POR and LVD reset must be released before the external

reset is released.).

<3> The TOOL0 pin is set to the high level.

<4> Setting of the flash memory programming mode by UART reception and complete the baud

rate setting.

Remarks 1. tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is

released during this period.

2. tSU: Time to release the external reset after the TOOL0 pin is set to the low level

3. tHD: Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the

processing time of the firmware to control the flash memory)

RESET

tSU

1 ms +

tHD

processing time

00H reception

(TOOLRXD, TOOLTXD mode)

<1>

<2>

<3>

<4>

TOOL0

･････

tSUINIT

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