Electronic Components Datasheet Search
  English  ▼

X  

F24 Datasheet(PDF) 152 Page - Renesas Technology Corp

Part # F24
Description  RENESAS MCU
PDF  210 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

F24 Datasheet(HTML) 152 Page - Renesas Technology Corp

Back Button F24 Datasheet HTML 148Page - Renesas Technology Corp F24 Datasheet HTML 149Page - Renesas Technology Corp F24 Datasheet HTML 150Page - Renesas Technology Corp F24 Datasheet HTML 151Page - Renesas Technology Corp F24 Datasheet HTML 152Page - Renesas Technology Corp F24 Datasheet HTML 153Page - Renesas Technology Corp F24 Datasheet HTML 154Page - Renesas Technology Corp F24 Datasheet HTML 155Page - Renesas Technology Corp F24 Datasheet HTML 156Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 152 / 210 page
background image
RL78/F23, F24
5. ELECTRICAL SPECIFICATIONS (GRADE 5)
R01DS0446EJ0120 Rev.1.20
Page 152 of 207
Dec 31, 2025
5.2.4 PLL Circuit Characteristics
(TA = -40 to +150
°C, 2.7 V ≤ EVDD0 = EVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Resonator
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
PLL input enable
clock frequency Note 1
fPLLI
fMAIN: 4.0 MHz
FMAINDIV[1:0] = 00B
3.92
4.0
4.08
MHz
fMAIN: 8.0 MHz
FMAINDIV[1:0] = 00B
7.84
8.0
8.16
MHz
fMAIN: 16.0 MHz
FMAINDIV[1:0] = 10B
7.84
8.0
8.16
MHz
fMAIN: 20.0 MHz
FMAINDIV[1:0] = 11B
4.90
5.0
5.10
MHz
PLL output frequency
(center value)
fPLL
fMAIN: 20MHz,
PLLMULA = 0, PLLMUL = 1
PLLDIV0 = 0, FPLLDIV = 0,
PLLDIV1 = 0
fPLLI × 16/2
MHz
PLLDIV0 = 0, FPLLDIV = 1,
PLLDIV1 = 1
fPLLI × 16
MHz
fMAIN: 4 MHz,
PLLMULA = 1, PLLMUL = 1
PLLDIV0 = 0, FPLLDIV = 0,
PLLDIV1 = 0
fPLLI × 20/2
MHz
PLLDIV0 = 0, FPLLDIV = 1,
PLLDIV1 = 1
fPLLI × 20
MHz
fMAIN: 8 MHz or 16 MHz,
PLLMULA = 0, PLLMUL = 0
PLLDIV0 = 1, FPLLDIV = 0,
PLLDIV1 = 0
fPLLI × 12/4
MHz
PLLDIV0 = 0, FPLLDIV = 0,
PLLDIV1 = 1
fPLLI × 12/2
MHz
fMAIN: 8 MHz or 16 MHz,
PLLMULA = 0, PLLMUL = 1
PLLDIV0 = 1, FPLLDIV = 0,
PLLDIV1 = 0
fPLLI × 16/4
MHz
PLLDIV0 = 0, FPLLDIV = 0,
PLLDIV1 = 1
fPLLI × 16/2
MHz
fMAIN: 8 MHz or 16 MHz,
PLLMULA = 1, PLLMUL = 0
PLLDIV0 = 0, FPLLDIV = 0,
PLLDIV1 = 0
fPLLI × 10/2
MHz
PLLDIV0 = 0, FPLLDIV = 1,
PLLDIV1 = 1
fPLLI × 10
MHz
Long-term jitter Note 2
tLJ
term = 1 μs
-1
+1
ns
term = 10 μs
-1
+1
ns
term = 20 μs
-2
+2
ns
Notes 1. If the high-speed on-chip oscillator clock is to be selected as the PLL input clock, the minimum and maximum
values will reflect the range of accuracy of the oscillation frequency by the high-speed on-chip oscillator clock.
2. Guaranteed by design, but not tested before shipment.
Remark fMAIN : Main system clock frequency.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com