LAN9313 datasheet(127/398 Pages) SMSC

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Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

127

Revision 1.2 (04-08-08)

DATASHEET

9.2.2

Write Sequence

In a write sequence, the host sends the 32-bit preamble, 2-bit start of frame, 2-bit op-code, 5-bit PHY

Address, 5-bit Register Address, 2-bit turn-around time, and finally the 16-bits of data. The MDIO pin

is three-stated throughout the write sequence.

The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD

transfer. No ordering requirement exists. The host may access either the low or high word first, as long

as the next write is performed to the opposite word. If a write to the same word is performed, the device

disregards the transfer.

Note:

SMI writes must not be performed to unused register addresses.

9.3

PHY Management Interface (PMI)

The PHY Management Interface (PMI) is used to access the internal PHYs as well as the external

PHY on the MII pins (in MAC modes only). The PMI operates at 2.5MHz, and implements the IEEE

802.3 management protocol, providing read/write commands for PHY configuration.

A read or write is performed using the frame format shown in Table 9.2. All addresses and data are

transferred msb first. Data bytes are transferred little endian.

Note 9.4

The turn-around time (TA) is used to avoid bus contention during a read cycle. For a read,

the external PHY drives the second bit of the turn-around time to 0, and then drives the

msb of the read data in the following cycle. For a write, the LAN9313/LAN9313i drives the

first bit of the turnaround time to 1, the second bit of the turnaround time to 0, and then

the msb of the write data in the following clock cycle.

Note 9.5

In the IDLE condition, the MDIO output is three-stated and pulled high externally.

The internal PHYs and optional external PHY (in MAC modes) are accessed via the PHY Management

Interface Access Register (PMI_ACCESS) and PHY Management Interface Data Register

(PMI_DATA). These registers allow read and write operations to all PHY registers. Refer to Section

13.1.6, "PHY Management Interface (PMI)," on page 207 for detailed information on these registers.

9.3.1

EEPROM Loader PHY Register Access

The PMI is also used by the EEPROM Loader to load the PHY registers with various configuration

strap values. The PHY Management Interface Access Register (PMI_ACCESS) and PHY Management

Interface Data Register (PMI_DATA) are also accessible as part of the Register Data burst sequence

of the EEPROM Loader. Refer to Section 8.2.4, "EEPROM Loader," on page 113 for additional

information.

Table 9.2 MII Management Frame Format

PREAMBLE

START

CODE

PHY

ADDRESS

TURN-

AROUND

TIME

Note 9.4

DATA

IDLE

Note

9.5

READ

32 1’s

AAAAA

RRRRR

DDDDDDDDDDDDDDDD

WRITE

32 1’s

AAAAA

RRRRR

DDDDDDDDDDDDDDDD

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