LAN9313 datasheet(125/398 Pages) SMSC

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Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

125

Revision 1.2 (04-08-08)

DATASHEET

Chapter 9 MII Management

9.1

Functional Overview

This chapter details the MII management functionality provided by the LAN9313/LAN9313i, which

includes the SMI Slave Controller, PHY Management Interface (PMI), and the MII Mode Multiplexer.

The SMI Slave Controller is used for CPU management of the LAN9313/LAN9313i via the MII pins,

and allows CPU access to all system CSRs. The PHY Management Interface (PMI) is used to access

the internal PHYs and optional external PHY, dependant on the management mode. The PMI

implements the IEEE 802.3 management protocol. The MII Mode Multiplexer is used to direct the

connections of the MII data path and MII management path based on the selected mode of the device.

9.2

SMI Slave Controller

The SMI slave controller uses the same pins and protocol as the IEEE 802.3 MII management function,

and differs only in that SMI provides access to all internal registers by using a non-standard extended

addressing map. The SMI protocol co-exists with the MII management protocol by using the upper half

of the PHY address space (16 through 31). All direct and indirect registers of the LAN9313/LAN9313i

can be accessed. The SMI management mode is selected when the mngt_mode_strap[1:0] inputs are

set to 01b. A list of management modes and their configuration settings are discussed in Section 2.3,

"Modes of Operation," on page 23.

The MII management protocol is limited to 16-bit data accesses. The protocol is also limited to 5 PHY

address bits and 5 register address bits. The SMI frame format can be seen in Table 9.1. The

LAN9313/LAN9313i uses the PHY Address field bits 3:0 as the system register address bits 9:6, and

the Register Address field as the system register address bits 5:1. Therefore, Register Address field

bit 0 is used as the upper/lower word select. The LAN9313/LAN9313i requires two back-to-back

accesses to each register (with alternate settings of Register Address field bit 0) which are combined

to form a 32-bit access. The access may be performed in any order.

Note:

When accessing the LAN9313/LAN9313i, the pair of cycles must be atomic. In this case, the

first host SMI cycle is performed to the low/high word and the second host SMI cycle is

performed to the high/low word, forming a 32-bit transaction with no cycles to the

LAN9313/LAN9313i in between. With the exception of Register Address field bit 0, all address

and control bits must be the same for both 16-bit cycles of a 32-bit transaction.

Input data on the MDIO pin is sampled on the rising edge of the MDC input clock. Output data is

sourced on the MDIO pin with the rising edge of the clock. The MDIO pin is three-stated unless actively

driving read data.

A read or a write is performed using the frame format shown in Table 9.1. All addresses and data are

transferred msb first. Data bytes are transferred little endian. When Register Address bit 0 is 1, bytes

3 & 2 are selected with byte 3 occurring first. When Register Address bit 0 is 0, bytes 1 & 0 are

selected with byte 1 occurring first.

Table 9.1 SMI Frame Format

PREAMBLE

START

CODE

PHY

ADDRESS

Note 9.1

ADDRESS

Note 9.1

TURN-

AROUND

TIME

Note 9.2

DATA

IDLE

Note

9.3

READ

32 1’s

1AAAA

9876

AAAAA

54321

DDDDDDDDDDDDDDDD

1111110000000000

5432109876543210

WRITE

32 1’s

1AAAA

9876

AAAAA

54321

DDDDDDDDDDDDDDDD

1111110000000000

5432109876543210

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