LAN9313 datasheet(123/398 Pages) SMSC

123 / 398 page

Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

123

Revision 1.2 (04-08-08)

DATASHEET

Figure 8.4 illustrates a typical single and multiple register read.

8.5.2.1

I2C Slave Read Polling for Reset Complete

During reset, the I2C slave interface will not return valid data. To determine when the reset condition

is complete, the Byte Order Test Register (BYTE_TEST) should be polled. Once the correct pattern is

read, the interface can be considered functional. At this point, the READY bit in the Hardware

Configuration Register (HW_CFG) can be polled to determine when the device initialization is

complete. Refer to Section 4.2, "Resets," on page 41 for additional information.

8.5.3

I2C Slave Write Sequence

Following the device addressing, as detailed in Section 8.5.1, a register is written to the

LAN9313/LAN9313i when the master continues to send data bytes. Each byte is acknowledged by the

LAN9313/LAN9313i. Following the fourth byte of the sequence, the master may either send another

start condition or halt the sequence with a stop condition. The internal register address is unchanged

following a single write.

Multiple writes are performed when the master sends additional bytes following the fourth

acknowledge. The internal address is automatically incremented and the next register is written. once

the internal address reaches it maximum value, it rolls over to 0. The multiple write is concluded when

the master sends another start condition or stop condition. The internal register address is incremented

for each write including the final. This is not relevant for subsequent writes, since a new register

address would be included on a new write cycle. However, this does affect the internal register address

if it were to be used for reads without first resetting the register address.

For both single and multiple writes, if the master sends an unexpected start or stop condition, the

LAN9313/LAN9313i will stop immediately and will respond to the next sequence as needed.

The data write to the register occurs after the 32-bits are input. In the event that 32-bits are not written

(master sends a start, or a stop condition occurs unexpectedly), the write is considered invalid and the

written after 32-bits. I2C writes must not be performed to unused register addresses.

Figure 8.4 I2C Slave Reads

Multiple Register Reads

Control Byte

Single Register Read

Data Byte...

Data Byte

Data 1 Byte

Address Byte

Control Byte

Address Byte

R/~W

...

Control Byte

...Data Byte

...Data m Byte

Data m+1 Byte... ...Data n Byte

LAN9313 Datasheet(PDF) 123 Page - SMSC Corporation

LAN9313 Datasheet(HTML) 123 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL