LAN9313 datasheet(121/398 Pages) SMSC

121 / 398 page

Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

121

Revision 1.2 (04-08-08)

DATASHEET

Figure 8.2 illustrates a typical single and multiple register write.

8.5

I2C Slave Operation

When in MAC/PHY I2C managed mode, the I2C slave interface is used for CPU management of the

LAN9313/LAN9313i. All system CSRs are accessible to the CPU in these modes. I2C mode is selected

when the mngt_mode_strap[1:0] inputs are set to 10b. The I2C slave controller implements the low

level I2C slave serial interface (start and stop condition detection, data bit transmission and reception,

and acknowledge generation and reception), handles the slave command protocol, and performs

system register reads and writes. The I2C slave controller conforms to the Philips I2C-Bus

Specification

The I2C slave serial interface consists of a data wire (SDA) and a serial clock (SCL). The serial clock

is driven by the master, while the data wire is bi-directional. Both signals are open-drain and require

external pull-up resistors. Both signals include Schmitt trigger inputs and digital input filters. The digital

filters reject pulses that are less than 100nS.

The I2C slave serial interface supports the standard-mode speed of up to 100KHz and the fast-mode

speed of 400KHz. Refer to the Philips I2C-Bus Specification for detailed I2C timing information.

8.5.1

I2C Slave Command Format

The I2C slave serial interface supports single register and multiple register read and write commands.

A read or write command is started by the master first sending a start condition, followed by a control

byte. The control byte consists of a 7-bit slave address and a 1-bit read/write indication (R/~W). The

slave address used by the LAN9313/LAN9313i is 0001010b, written as SA6 (first bit on the wire)

through SA0 (last bit on the wire). Assuming the slave address in the control byte matches this

address, the control byte is acknowledged by the LAN9313/LAN9313i. Otherwise, the entire sequence

is ignored until the next start condition. The I2C command format can be seen in Figure 8.3.

If the read/write indication (R/~W) in the control byte is a 0 (indicating a potential write), the next byte

sent by the master is the register address. After the address byte is acknowledged by the

Figure 8.2 SPI Writes

Single Register Write

000

Instruction

Address

Data

Multiple Register Writes

000

Instruction

dec

Address

inc

...

SCK (active high)

nSCS

SCK (active low)

SCK (active high)

nSCS

SCK (active low)

Data 1...

...Data m

...Data m+1

...Data n

LAN9313 Datasheet(PDF) 121 Page - SMSC Corporation

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