LAN9313 datasheet(208/398 Pages) SMSC

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Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

Revision 1.2 (04-08-08)

208

SMSC LAN9313/LAN9313i

DATASHEET

13.1.6.2

PHY Management Interface Access Register (PMI_ACCESS)

This register is used to control the management cycles to the PHYs. A PHY access is initiated when

this register is written. This register is used in conjunction with the PHY Management Interface Data

Note:

The Virtual PHY registers are NOT accessible via these registers.

Offset:

0A8h

Size:

32 bits

BITS

DESCRIPTION

TYPE

DEFAULT

31:16

RESERVED

15:11

PHY Address (PHY_ADDR)

These bits select the PHY device being accessed. Refer to Section 7.1.1,

"PHY Addressing," on page 84 for information on PHY address

assignments.

R/W

00000b

10:6

MII Register Index (MIIRINDA)

These bits select the desired MII register in the PHY. Refer to Section 13.2,

"Ethernet PHY Control and Status Registers," on page 231 for detailed

descriptions on all PHY registers.

R/W

00000b

5:2

RESERVED

MII Write (MIIWnR)

Setting this bit informs the PHY that the access will be a write operation

using the PHY Management Interface Data Register (PMI_DATA). If this bit

is cleared, the access will be a read operation, returning data into the PHY

Management Interface Data Register (PMI_DATA).

R/W

MII Busy (MIIBZY)

This bit must be read as 0 before writing to the PHY Management Interface

Data Register (PMI_DATA) or PHY Management Interface Access Register

(PMI_ACCESS) registers. This bit is automatically set when this register is

written. During a PHY register access, this bit will be set, signifying a read

or write access is in progress. This is a self-clearing (SC) bit that will return

to 0 when the PHY register access has completed.

During a PHY register write, the PHY Management Interface Data Register

(PMI_DATA) must be kept valid until this bit is cleared.

During a PHY register read, the PHY Management Interface Data Register

(PMI_DATA) register is invalid until the MAC has cleared this bit.

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