C167CS datasheet(304/517 Pages) INFINEON

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C167CS

Derivatives

The Watchdog Timer (WDT)

User’s Manual

13-4

V2.0, 2000-07

protected instructions the Protection Fault Trap will be entered, rather than the

instruction be executed.

Note: The reset value depends on the reset source (see description below).

The execution of EINIT clears the reset indication flags.

The time period for an overflow of the watchdog timer is programmable in two ways:

• The input frequency to the watchdog timer can be selected via a prescaler controlled

by bits WDTPRE and WDTIN in register WDTCON to be

fCPU / 2, fCPU / 4, fCPU / 128, or fCPU / 256.

• The reload value WDTREL for the high byte of WDT can be programmed in register

WDTCON.

The period PWDT between servicing the watchdog timer and the next overflow can

therefore be determined by the following formula:

WDTCON

WDT Control Register

SFR (FFAEH/D7H)

Reset Value: 00XXH

98765

43210

WDTREL

WDT

PRE

LHW

SHW

WDT

Bit

Function

WDTIN

Watchdog Timer Input Frequency Select

Controls the input clock prescaler. See Table 13-1.

WDTR

Watchdog Timer Reset Indication Flag

Cleared by a hardware reset or by the SRVWDT instruction.

SWR

Software Reset Indication Flag

SHWR

Short Hardware Reset Indication Flag

LHWR

Long Hardware Reset Indication Flag

WDTPRE

Watchdog Timer Input Prescaler Control

Controls the input clock prescaler. See Table 13-1.

WDTREL

Watchdog Timer Reload Value (for the high byte of WDT)

PWDT =

fCPU

2(1 + <WDTPRE> + <WDTIN> × 6)

× (216 – <WDTREL> × 28)

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