C167CS datasheet(326/517 Pages) INFINEON

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C167CS

Derivatives

The Capture/Compare Units

User’s Manual

16-8

V2.0, 2000-07

Counter Mode

The bits TxM in SFRs T01CON and T78CON select between timer or counter mode for

the respective timer. In Counter mode (TxM = ‘1’) the input clock for a timer can be

derived from the overflows/underflows of timer T6 in block GPT2. In addition, timers T0

and T7 can be clocked by external events. Either a positive, a negative, or both a positive

and a negative transition at pin T0IN or T7IN (alternate port input function), respectively,

can be selected to cause an increment of T0/T7.

When T1 or T8 is programmed to run in counter mode, bit field TxI is used to enable the

overflows/underflows of timer T6 as the count source. This is the only option for these

timers and it is selected by the combination TxI = 000B. When bit field TxI is programmed

to any other valid combination, the respective timer will stop.

When T0 or T7 is programmed to run in counter mode, bit field TxI is used to select the

count source and transition (if the source is the input pin) which should cause a count

trigger (see description of TxyCON for the possible selections).

Note: In order to use pin T0IN or T7IN as external count input pin, the respective port pin

must be configured as input, i.e. the corresponding direction control bit must be

cleared (DPx.y = ‘0’).

If the respective port pin is configured as output, the associated timer may be

clocked by modifying the port output latches Px.y via software, e.g. for testing

purposes.

The maximum external input frequency to T0 or T7 in counter mode is

fCPU/16. To

ensure that a signal transition is properly recognized at the timer input, an external count

input signal should be held for at least 8 CPU clock cycles before it changes its level

again. The incremented count value appears in SFR T0/T7 within 8 CPU clock cycles

after the signal transition at pin TxIN.

Reload

A reload of a timer with the 16-bit value stored in its associated reload register in both

modes is performed each time a timer would overflow from FFFFH to 0000H. In this case

the timer does not wrap around to 0000H, but rather is reloaded with the contents of the

respective reload register TxREL. The timer then resumes incrementing starting from the

reloaded value.

The reload registers TxREL are not bitaddressable.

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