C167CS datasheet(344/517 Pages) INFINEON

344 / 517 page

C167CS

Derivatives

The Pulse Width Modulation Module

User’s Manual

17-3

V2.0, 2000-07

Mode 0: Standard PWM Generation (Edge Aligned PWM)

Mode 0 is selected by clearing the respective bit PMx in register PWMCON1 to ‘0’. In

this mode the timer PTx of the respective PWM channel is always counting up until it

reaches the value in the associated period shadow register. Upon the next count pulse

the timer is reset to 0000H and continues counting up with subsequent count pulses. The

PWM output signal is switched to high level when the timer contents are equal to or

greater than the contents of the pulse width shadow register. The signal is switched back

to low level when the respective timer is reset to 0000H, i.e. below the pulse width

shadow register. The period of the resulting PWM signal is determined by the value of

the respective PPx shadow register plus 1, counted in units of the timer resolution.

PWM_PeriodMode0 = [PPx] + 1

The duty cycle of the PWM output signal is controlled by the value in the respective pulse

width shadow register. This mechanism allows the selection of duty cycles from 0% to

100% including the boundaries. For a value of 0000H the output will remain at a high

level, representing a duty cycle of 100%. For a value higher than the value in the period

Figure 17-3 illustrates the operation and output waveforms of a PWM channel in mode 0

for different values in the pulse width register. This mode is referred to as Edge Aligned

PWM, because the value in the pulse width (shadow) register only effects the positive

edge of the output signal. The negative edge is always fixed and related to the clearing

of the timer.

C167CS Datasheet(PDF) 344 Page - Infineon Technologies AG