C167CS datasheet(206/517 Pages) INFINEON

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C167CS

Derivatives

The External Bus Interface

User’s Manual

9-18

V2.0, 2000-07

9.4

READY Controlled Bus Cycles

For situations, where the programmable waitstates are not enough, or where the

response (access) time of a peripheral is not constant, the C167CS provides external

bus cycles that are terminated via a READY input signal (synchronous or

asynchronous). In this case the C167CS first inserts a programmable number of

waitstates (0 … 7) and then monitors the READY line to determine the actual end of the

current bus cycle. The external device drives READY low in order to indicate that data

have been latched (write cycle) or are available (read cycle).

Figure 9-10

READY Controlled Bus Cycles

The READY function is enabled via the RDYENx bits in the BUSCON registers. When

this function is selected (RDYENx = ‘1’), only the lower 3 bits of the respective MCTC bit

field define the number of inserted waitstates (0 … 7), while the MSB of bit field MCTC

selects the READY operation:

MCTC.3 = ‘0’: Synchronous READY, i.e. the READY signal must meet setup and hold

times.

MCTC.3 = ‘1’: Asynchronous READY, i.e. the READY signal is synchronized internally.

Evaluation (sampling) of the READY input

AREADY

SREADY

RD/WR

ALE

2. WS

with active READY

1. WS

Bus Cycle

MCD02237

extended via READY

1. WS

2. WS

Bus Cycle

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