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C167CS Datasheet(PDF) 202 Page - Infineon Technologies AG |
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C167CS Datasheet(HTML) 202 Page - Infineon Technologies AG |
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202 / 517 page ![]() C167CS Derivatives The External Bus Interface User’s Manual 9-14 V2.0, 2000-07 Programmable Memory Cycle Time The C167CS allows the user to adjust the controller’s external bus cycles to the access time of the respective memory or peripheral. This access time is the total time required to move the data to the destination. It represents the period of time during which the controller’s signals do not change. Figure 9-7 Memory Cycle Time The external bus cycles of the C167CS can be extended for a memory or peripheral, which cannot keep pace with the controller’s maximum speed, by introducing wait states during the access (see Figure 9-7). During these memory cycle time wait states, the CPU is idle, if this access is required for the execution of the current instruction. The memory cycle time wait states can be programmed in increments of one CPU clock (2 TCL) within a range from 0 to 15 (default after reset) via the MCTC fields of the BUSCON registers. 15 – <MCTC> waitstates will be inserted. MCT02063 Address Segment ALE BUS (P0) Address RD Address Data BUS (P0) WR MCTC Wait States (1...15) Bus Cycle Data/Instr. |
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