C167CS datasheet(199/517 Pages) INFINEON

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C167CS

Derivatives

The External Bus Interface

User’s Manual

9-11

V2.0, 2000-07

Read or Write Chip Select signals remain active only as long as the associated control

signal (RD or WR) is active. This also includes the programmable read/write delay. Read

chip select is only activated for read cycles, write chip select is only activated for write

cycles, read/write chip select is activated for both read and write cycles (write cycles are

assumed, if any of the signals WRH or WRL gets active). These modes save external

glue logic, when accessing external devices like latches or drivers that only provide a

single enable input.

Address Chip Select signals remain active during the complete bus cycle. For address

chip select signals two generation modes can be selected via bit CSCFG in register

SYSCON:

•A latched address chip select signal (CSCFG = ‘0’) becomes active with the falling

edge of ALE and becomes inactive at the beginning of an external bus cycle that

accesses a different address window. No spikes will be generated on the chip select

lines and no changes occur as long as locations within the same address window or

within internal memory (excluding X-Peripherals and XRAM) are accessed.

•An early address chip select signal (CSCFG = ‘1’) becomes active together with the

address and BHE (if enabled) and remains active until the end of the current bus

cycle. Early address chip select signals are not latched internally and may toggle

intermediately while the address is changing.

Note: CS0 provides a latched address chip select directly after reset (except for single

chip mode) when the first instruction is fetched.

Internal pullup devices hold all CS lines high during reset. After the end of a reset

sequence the pullup devices are switched off and the pin drivers control the pin levels

on the selected CS lines. Not selected CS lines will enter the high-impedance state and

are available for general purpose IO.

The pullup devices are also active during bus hold on the selected CS lines, while HLDA

is active and the respective pin is switched to push/pull mode. Open drain outputs will

float during bus hold. In this case external pullup devices are required or the new bus

master is responsible for driving appropriate levels on the CS lines.

Segment Address versus Chip Select

The external bus interface of the C167CS supports many configurations for the external

memory. By increasing the number of segment address lines the C167CS can address

a linear address space of 256 KByte, 1 MByte or 16 MByte. This allows to implement a

large sequential memory area, and also allows to access a great number of external

devices, using an external decoder. By increasing the number of CS lines the C167CS

can access memory banks or peripherals without external glue logic. These two features

may be combined to optimize the overall system performance.

Note: Bit SGTDIS of register SYSCON defines, if the CSP register is saved during

interrupt entry (segmentation active) or not (segmentation disabled).

C167CS Datasheet(PDF) 199 Page - Infineon Technologies AG

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