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C167CS Datasheet(PDF) 201 Page - Infineon Technologies AG

Part # C167CS
Description  16-Bit Single-Chip Microcontroller
PDF  517 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

C167CS Datasheet(HTML) 201 Page - Infineon Technologies AG

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C167CS
Derivatives
The External Bus Interface
User’s Manual
9-13
V2.0, 2000-07
ALE Length Control
The length of the ALE signal and the address hold time after its falling edge are
controlled by the ALECTLx bits in the BUSCON registers. When bit ALECTL is set to ‘1’,
external bus cycles accessing the respective address window will have their ALE signal
prolonged by half a CPU clock (1 TCL). Also the address hold time after the falling edge
of ALE (on a multiplexed bus) will be prolonged by half a CPU clock, so the data transfer
within a bus cycle refers to the same CLKOUT edges as usual (i.e. the data transfer is
delayed by one CPU clock). This allows more time for the address to be latched.
Note: ALECTL0 is ‘1’ after reset to select the slowest possible bus cycle, the other
ALECTLx are ‘0’ after reset.
Figure 9-6
ALE Length Control
Setup
(P0)
WR
BUS
Address
Data
(P0)
BUS
RD
(P4)
ALE
Segment
Normal Multiplexed
Bus Cycle
Address
Address
Data/Instr.
Address
Data
MCD02235
Lengthened Multiplexed
Bus Cycle
Address
Address
Hold
Data/Instr.



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