C167CS datasheet(204/517 Pages) INFINEON

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C167CS

Derivatives

The External Bus Interface

User’s Manual

9-16

V2.0, 2000-07

Read/Write Signal Delay

The C167CS allows the user to adjust the timing of the read and write commands to

account for timing requirements of external peripherals. The read/write delay controls

the time between the falling edge of ALE and the falling edge of the command. Without

read/write delay the falling edges of ALE and command(s) are coincident (except for

propagation delays). With the delay enabled, the command(s) become active half a CPU

clock (1 TCL) after the falling edge of ALE.

The read/write delay does not extend the memory cycle time, and does not slow down

the controller in general. In multiplexed bus modes, however, the data drivers of an

external device may conflict with the C167CS’s address, when the early RD signal is

used. Therefore multiplexed bus cycles should always be programmed with read/write

delay.

The read/write delay is controlled via the RWDCx bits in the BUSCON registers. The

command(s) will be delayed, if bit RWDCx is ‘0’ (default after reset).

Early WR Signal Deactivation

The duration of an external write access can be shortened by one TCL. The WR signal

is activated (driven low) in the standard way, but can be deactivated (driven high) one

TCL earlier than defined in the standard timing. In this case also the data output drivers

will be deactivated one TCL earlier.

This is especially useful in systems which operate on higher CPU clock frequencies and

employ external modules (memories, peripherals, etc.) which switch on their own data

drivers very fast in response to e.g. a chip select signal.

Conflicts between the C167CS’s and the external peripheral’s output drivers can be

avoided then by selecting early WR for the C167CS.

Note: Make sure that the reduced WR low time then still matches the requirements of

the external peripheral/memory.

Early WR deactivation is controlled via the EWENx bits in the BUSCON registers. The

WR signal will be shortened if bit EWENx is ‘1’ (default after reset is a standard WR

signal, i.e. EWENx = ‘0’).

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