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C167CS Datasheet(PDF) 208 Page - Infineon Technologies AG |
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C167CS Datasheet(HTML) 208 Page - Infineon Technologies AG |
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208 / 517 page  C167CS Derivatives The External Bus Interface User’s Manual 9-20 V2.0, 2000-07 9.5 Controlling the External Bus Controller A set of registers controls the functions of the EBC. General features like the usage of interface pins (WR, BHE), segmentation and internal ROM mapping are controlled via register SYSCON. The properties of a bus cycle like chip select mode, usage of READY, length of ALE, external bus mode, read/write delay and waitstates are controlled via registers BUSCON4 … BUSCON0. Four of these registers (BUSCON4 … BUSCON1) have an address select register (ADDRSEL4 … ADDRSEL1) associated with them, which allows to specify up to four address areas and the individual bus characteristics within these areas. All accesses that are not covered by these four areas are then controlled via BUSCON0. This allows to use memory components or peripherals with different interfaces within the same system, while optimizing accesses to each of them. SYSCON System Control Register SFR (FF12H/89H) Reset Value: 0XX0H 15 14 13 12 11 10 9 876 5432 1 0 STKSZ ROM S1 SGT DIS ROM EN BYT DIS CLK EN WR CFG CS CFG - OWD DIS BD RST EN XPEN VISI- BLE XPER SHA-RE rw rw rw rwh rwh rw rwh rw - rwh rw rw rw rw Bit Function XPER-SHARE XBUS Peripheral Share Mode Control 0: External accesses to XBUS peripherals are disabled 1: XBUS peripherals are accessible via the ext. bus during hold mode VISIBLE Visible Mode Control 0: Accesses to XBUS peripherals are done internally 1: XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable Bit 0: Accesses to the on-chip X-Peripherals and their functions are disabled 1: The on-chip X-Peripherals are enabled and can be accessed BDRSTEN Bidirectional Reset Enable Bit 0: Pin RSTIN is an input only. 1: Pin RSTIN is pulled low during the internal reset sequence after any reset. OWDDIS Oscillator Watchdog Disable Bit (Configured via pin RD upon a reset) 0: The on-chip oscillator watchdog is enabled and active. 1: The on-chip oscillator watchdog is disabled and the CPU clock is always fed from the oscillator input. |
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