C167CS datasheet(195/517 Pages) INFINEON

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C167CS

Derivatives

The External Bus Interface

User’s Manual

9-7

V2.0, 2000-07

multiplexed bus modes the address is also required on PORT0. In this special case the

address on PORT0 is delayed by one CPU clock cycle, which delays the complete

(multiplexed) bus cycle and extends the corresponding ALE signal (see Figure 9-4).

This extra time is required to allow the previously selected device (via demultiplexed

bus) to release the data bus, which would be available in a demultiplexed bus cycle.

Figure 9-4

Switching from Demultiplexed to Multiplexed Bus Mode

Switching between external resources (e.g. different peripherals) may incur a

problem if the previously accessed resource needs some time to switch of its output

drivers (after a read) and the resource to be accessed next switches on its output drivers

very fast. In systems running on higher frequencies this may lead to a bus conflict (the

switch off delays normally are independent from the clock frequency).

In such a case an additional waitstate can automatically be inserted when leaving a

certain address window, i.e. when the next cycle accesses a different window. This

waitstate is controlled in the same way as the waitstate when switching from

demultiplexed to multiplexed bus mode, see Figure 9-4.

BUSCON switch waitstates are enabled via bits BSWCx in the BUSCON registers. By

enabling the automatic BUSCON switch waitstate (BSWCx = ‘1’) there is no impact on

the system performance as long as the external bus cycles access the same address

window. Only if the following cycle accesses a different window a waitstate is inserted

between the last access to the previous window and the first access to the new window.

After reset no BUSCON switch waitstates are selected.

MCD02234

Address

Data/Instr.

Address

Data

Bus Cycle

Address

Address (P1)

ALE

Data

Segment (P4)

Bus Cycle

BUS (P0)

Demultiplexed

Multiplexed

Idle State

Data/Instr.

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