C167CS datasheet(192/517 Pages) INFINEON

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C167CS

Derivatives

The External Bus Interface

User’s Manual

9-4

V2.0, 2000-07

Multiplexed Bus Modes

In the multiplexed bus modes the 16-bit intra-segment address as well as the data use

PORT0. The address is time-multiplexed with the data and has to be latched externally.

The width of the required latch depends on the selected data bus width, i.e. an 8-bit data

bus requires a byte latch (the address bits A15 … A8 on P0H do not change, while P0L

multiplexes address and data), a 16-bit data bus requires a word latch (the least

significant address line A0 is not relevant for word accesses).

The upper address lines (An … A16) are permanently output on Port 4 (if segmentation

is enabled) and do not require latches.

The EBC initiates an external access by generating the Address Latch Enable signal

(ALE) and then placing an address on the bus. The falling edge of ALE triggers an

external latch to capture the address. After a period of time during which the address

must have been latched externally, the address is removed from the bus. The EBC now

activates the respective command signal (RD, WR, WRL, WRH). Data is driven onto the

bus either by the EBC (for write cycles) or by the external memory/peripheral (for read

cycles). After a period of time, which is determined by the access time of the memory/

peripheral, data become valid.

Read cycles: Input data is latched and the command signal is now deactivated. This

causes the accessed device to remove its data from the bus which is then tri-stated

again.

Write cycles: The command signal is now deactivated. The data remain valid on the bus

until the next external bus cycle is started.

Figure 9-2

Multiplexed Bus Cycle

MCT02060

Address

Segment (P4)

ALE

BUS (P0)

Data/Instr.

Address

Data

BUS (P0)

Bus Cycle

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