C167CS datasheet(193/517 Pages) INFINEON

193 / 517 page

C167CS

Derivatives

The External Bus Interface

User’s Manual

9-5

V2.0, 2000-07

Demultiplexed Bus Modes

In the demultiplexed bus modes the 16-bit intra-segment address is permanently output

on PORT1, while the data uses PORT0 (16-bit data) or P0L (8-bit data).

The upper address lines are permanently output on Port 4 (if selected via SALSEL

during reset). No address latches are required.

The EBC initiates an external access by placing an address on the address bus. After a

programmable period of time the EBC activates the respective command signal (RD,

WR, WRL, WRH). Data is driven onto the data bus either by the EBC (for write cycles)

or by the external memory/peripheral (for read cycles). After a period of time, which is

determined by the access time of the memory/peripheral, data become valid.

Read cycles: Input data is latched and the command signal is now deactivated. This

causes the accessed device to remove its data from the data bus which is then tri-stated

again.

Write cycles: The command signal is now deactivated. If a subsequent external bus

cycle is required, the EBC places the respective address on the address bus. The data

remain valid on the bus until the next external bus cycle is started.

Figure 9-3

Demultiplexed Bus Cycle

MCD02061

Address

Address (P1)

ALE

BUS (P0)

Data

BUS (P0)

Segment (P4)

Bus Cycle

Data/Instr.

C167CS Datasheet(PDF) 193 Page - Infineon Technologies AG