C167CS datasheet(235/517 Pages) INFINEON

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C167CS

Derivatives

The General Purpose Timer Units

User’s Manual

10-7

V2.0, 2000-07

Timer 3 in Gated Timer Mode

Gated timer mode for the core timer T3 is selected by setting bit field T3M in register

T3CON to ‘010B’ or ‘011B’. Bit T3M.0 (T3CON.3) selects the active level of the gate

input. In gated timer mode the same options for the input frequency as for the timer mode

are available. However, the input clock to the timer in this mode is gated by the external

input pin T3IN (Timer T3 External Input).

To enable this operation pin T3IN must be configured as input, i.e. the corresponding

direction control bit must contain ‘0’.

Figure 10-4

Block Diagram of Core Timer T3 in Gated Timer Mode

If T3M.0 = ‘0’, the timer is enabled when T3IN shows a low level. A high level at this pin

stops the timer. If T3M.0 = ‘1’, pin T3IN must have a high level in order to enable the

timer. In addition, the timer can be turned on or off by software using bit T3R. The timer

will only run, if T3R = ‘1’ and the gate is active. It will stop, if either T3R = ‘0’ or the gate

is inactive.

Note: A transition of the gate signal at pin T3IN does not cause an interrupt request.

MUX

Core Timer Tx

TxOTL

Interrupt

Request

TxOE

TxOUT

TxR

XOR

MUX

Up/

Down

TxEUD

TxUDE

MCB02029

TxUD

2n : 1

TxI

CPU

TxM

TxIN

T3IN = P3.6

T3EUD = P3.4

x = 3

T3OUT = P3.3

n = 3 … 10

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