C167CS datasheet(236/517 Pages) INFINEON

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C167CS

Derivatives

The General Purpose Timer Units

User’s Manual

10-8

V2.0, 2000-07

Timer 3 in Counter Mode

Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON

to ‘001B’. In counter mode timer T3 is clocked by a transition at the external input pin

T3IN. The event causing an increment or decrement of the timer can be a positive, a

negative, or both a positive and a negative transition at this pin. Bit field T3I in control

Figure 10-5

Block Diagram of Core Timer T3 in Counter Mode

For counter operation, pin T3IN must be configured as input, i.e. the respective direction

control bit DPx.y must be ‘0’. The maximum input frequency which is allowed in counter

mode is

fCPU/16. To ensure that a transition of the count input signal which is applied to

T3IN is correctly recognized, its level should be held high or low for at least 8

fCPU cycles

before it changes.

Table 10-5

GPT1 Core Timer T3 (Counter Mode) Input Edge Selection

T3I

Triggering Edge for Counter Increment/Decrement

0 0 0

None. Counter T3 is disabled

0 0 1

Positive transition (rising edge) on T3IN

0 1 0

Negative transition (falling edge) on T3IN

0 1 1

Any transition (rising or falling edge) on T3IN

1 X X

Reserved. Do not use this combination

Core Timer Tx

TxR

XOR

MUX

Up/

Down

TxEUD

TxUDE

MCB02030

TxUD

Txl

TxIN

Edge

Select

TxOTL

TxOE

TxOUT

Interrupt

Request

T3IN = P3.6

T3EUD = P3.4

T3OUT = P3.3

x = 3

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