38D2 datasheet(132/136 Pages) RENESAS

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REVISION HISTORY

38D2 Group Datasheet

Rev.

Date

Description

Page

Summary

1.00

Jan. 23, 2006

−

First edition issued

2.00

Mar. 24, 2006

FEATURES : Description of reset circuit eliminated and Power source voltage

revised.

Performance overview: Oscillation frequency and Power source voltage revised.

FUNCTIONAL BLOCK DIAGRAM : Description of reset circuit eliminated.

Fig. 4 and Table 3 38D29GC, 38D29G8 added.

Fig. 9 Memory map diagram revised.

Table 7 Non-port function of port P54

−P57 revised.

Related SFRs of port P40 and P41 revised.

Fig. 15 (18) Port P61 revised.

Fig. 22 Timer 12 mode register revised.

Notes on Timer X: (1), (2) revised.

• Real Time Port Control revised.

Fig. 32 UART control register revised.

Fig. 34 Note 1 revised.

Fig. 38 Note 2 revised.

Fig. 46 Memory map revised.

Note 1 revised.

Clock output function revised.

Reset circuit revised.

(1)Stop mode: Description revised.

Fig. 58

φSOURCE added.

Fig. 60 State transitions of system clock: Note 3 revised.

Address of oscillation ouput control register revised.

Fig. 64 Connection of XIN and XOUT revised.

65-75

Electrical characteristics added.

2.01

Nov. 15, 2006

DESCRIOTION revised

Power dissipation described.

Main clock / Sub-clock generating circuits: Built-in feed back resistor

→ Built-in

Power dissipation described.

5AVSS: GND input pin

→ Analog power source input pin

ROM and ROM Code Protect Address : Description revised.

Fig. 9 is revised.

Table 7 : As for CKOUT, non-port function and related SFRs are added.

Termination of unused pins : As for I/O ports, description added.

VL3 : Terminations 1 and 2 revised.

Timer 1, Timer 2 : Description revised.

Timer X : Description revised.

Fig. 24 : TXCON1 bit 5 = 1

→ TXCON1 bit 5 = 0

Timer Y : Description revised.

Fig. 26 : Note added.

Fig. 33 : Note and

φ source added.

REVISION HISTORY

38D2 Datasheet(PDF) 132 Page - Renesas Technology Corp

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