38D2 datasheet(128/136 Pages) RENESAS

128 / 136 page

Rev.3.02

Apr 10, 2008

Page 128 of 131

REJ03B0177-0302

38D2 Group

Notes on Flash Memory Mode

• CPU Rewrite Mode

(1) Operating Speed

During CPU rewrite mode, set the system clock

φ to 4.0 MHz or

less using the main clock division ratio selection bits (bits 6 and

7 of address 003B16).

(2) Prohibited Instructions

During CPU rewrite mode, the instructions which reference data

in the flash memory cannot be used.

(3) Interrupts

During CPU rewrite mode, interrupts cannot be used because

they reference data in the flash memory.

(4) Watchdog Timer

If the watchdog timer has been running already, the internal reset

by underflow will not occur because the watchdog timer is

continuously cleared during program or erase operation.

(5) Reset

Reset is always valid. If CNVSS = “H” when a reset is released,

boot mode is active. The program starts from the address stored

in addresses FFFC16 and FFFD16 in boot ROM area.

Notes on Watchdog Timer

1. Watchdog Timer Underflow

The watchdog timer does not operate in stop mode, but it

continues counting during the wait time to release the stop state

and in wait mode. Write to the watchdog timer control register so

that the watchdog timer will not underflow during these periods.

2. Stopping On-Chip Oscillator Oscillation

When the on-chip oscillator is selected by the watchdog timer

count source selection bit 2, the on-chip oscillator forcibly

oscillates and it cannot be stopped. Also, in this time, set the STP

instruction function selection bit to “1” at this time.

Select “0” (

φSOURCE) for the watchdog timer count source

selection bit 2 at the system which on-chip oscillator is stopped.

3. Watchdog Timer Control Register

Bits 7 to 5 can be rewritten only once after a reset. After writing,

rewriting is disabled because they are locked. These bits are set

to “0” after a reset.

Notes on Differences between QzROM Version and

Flash Memory Version

The flash memory and QzROM versions differ in their

manufacturing processes, built-in ROM, memory size, and

layout patterns. Because of these differences, characteristic

values, operation margins, noise immunity, and noise radiation

and oscillation circuit constants may vary within the specified

range of electrical characteristics.

When switching to the QzROM version, implement system

evaluations equivalent to those performed in the flash memory

version.

Confirm page 11 about the differences of functions.

Notes on Power Source Voltage

When the power supply voltage value of the MCU is less than

the value indicated in the recommended operating conditions, the

MCU may not operate normally and perform unstable operation.

In a system where the power source voltage drops slowly when

the power source voltage drops or the power is turned off, reset

the MCU when the power source voltage is less than the

recommended operating conditions, and design the system so

that this unstable operation does not cause errors to it.

Notes on Handling Power Source Pins

Before using the MCU, connect a capacitor suitable for high

frequencies as a bypass capacitor between the following:

The power source pin (VCC pin) and the GND pin (VSS pin)

The power source pin (VCC pin) and the analog power source

input pin (AVSS pin). As a bypass capacitor, a ceramic capacitor

of 0.01

μF to 0.1 μF is recommended.

Also, use the shortest possible wiring to connect a bypass

capacitor between the power source pin and the GND pin and

between the power source pin and the analog power source pin.

Notes on Memory

1. RAM

The RAM content is undefined at a reset. Be sure to set the initial

value before use.

38D2 Datasheet(PDF) 128 Page - Renesas Technology Corp

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