38D2 datasheet(124/136 Pages) RENESAS

124 / 136 page

Rev.3.02

Apr 10, 2008

Page 124 of 131

REJ03B0177-0302

38D2 Group

Notes on Serial I/O1

Becaouse the operation of the serial I/O2 is as same as serial

I/O1, the following notes are written about the serial I/O1.

1. Write to Baud Rate Generator

Write to the baud rate generator while transmission/reception is

stopped.

2. Setting Sequence When Serial I/O1 Transmit

Interrupt Used

To use the serial I/O1 transmit interrupt, if the interrupt

occurrence synchronized with settings is not required, take the

following sequence:

(1) Set the serial I/O1 transmit interrupt enable bit (bit 2 of

interrupt control register 2 (address 003F16)) to “0”

(disabled).

(2) Set the transmit enable bit to “1”.

(3) After one or more instructions have been executed, set the

serial I/O1 transmit interrupt request bit (bit 2 of interrupt

request register 2 (address 003D16)) to “0” (no interrupt).

(4) Set the serial I/O1 transmit interrupt enable bit to “1”

(enabled).

When the transmit enable bit is set to “1”, the transmit buffer

empty flag (bit 0 of serial I/O1 status register) and the transmit

shift completion flag are set to “1”.

This allows an interrupt request to be generated regardless of

which interrupt occurrence source has been selected by the

transmit interrupt source selection bit (bit 3 of serial I/O1 control

“1”.

3. Data Transmission Control Using Transmit Shift

Completion Flag

After transmit data is written to the transmit buffer register, the

transmit shift completion flag (bit 2 of serial I/O1 status register

(address 001916)) changes from “1” to “0” after a delay of 0.5 to

1.5 cycles of the system clock. Thus, after transmit data is written

to the transmit buffer register, note this delay when controlling

data transmission by referencing the transmit shift completion

flag.

4. Setting Serial I/O1 Control Register

Before setting the serial I/O1 control register again, first set both

the transmit enable bit and the receive enable bit to “0” and

initialize the transmission and reception circuits.

Fig. 103 Sequence of setting serial I/O1 control register

5. Pin Status After Transmission Completed

After transmission is completed, the TxD pin retains the level

when transmission is completed.

When the internal clock is selected in clock synchronous serial

I/O mode, the SCLK1 pin is set to “H”.

6. Serial I/O1 Enable Bit during Transmit Operation

During transmission, if the serial I/O1 enable bit (bit 7 of serial

I/O1 control register (address 001A16)) is set to “0”, the pin

function is set to an I/O port and the internal transmit operation

continues even though transmit data is not output externally.

Also, if the transmit buffer register is written in this state,

transmit operation starts internally. If the serial I/O1 enable bit is

set to “1” at this time, transmit data is output to the TxD pin from

that point.

7. Transmission

Control

When

External

Clock

Selected

During data transmission, if the external clock is selected as the

synchronous clock, set the transmit enable bit to “1” while SCLK1

is set to “H”. Also, write to the transmit buffer register while

SCLK1 is set to “H”.

8. Receive Operation in Clock Synchronous Serial I/O

Mode

During reception in clock synchronous serial I/O mode, set both

the transmit enable bit and the receive enable bit to “1”. Then

write dummy data to the transmit buffer register. When the

internal clock is selected as the synchronous clock, the

synchronous clock is output at this point and receive operation

starts. When the external clock is selected, reception is enabled at

this point and inputting the external clock starts transmit

operation.

The P55/TXD1 [P32/TxD2] pin outputs dummy data written in the

transmit buffer register.

9. Transmit/Receive Operation in Clock Synchronous

Serial I/O Mode

In clock synchronous serial I/O mode, set the transmit enable bit

and the receive enable bit to “0” simultaneously to stop

transmit/receive operations. If only one of the operations is

stopped, transmission and reception cannot be synchronized,

which will cause a bit error.

Set bits 0 to 3, and 6 of the serial I/O1 control

Set both the transmit enable bit (TE) and the

receive enable bit (RE) to “0”

Set both the transmit enable bit (TE) and the receive

enable bit (RE), or one of them to “1”.

Settings can be made with

the LDM instruction at the

same time

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