7641 datasheet(38/138 Pages) RENESAS

38 / 138 page

7641 Group

Rev.4.00

Aug 28, 2006

page 38 of 135

REJ03B0191-0400

Fig. 31 DMACx (x = 0, 1) block diagram

DMAC

The 7641 group is equipped with 2 channels of DMAC (direct

memory access controller) which enable high speed data transfer

from a memory to a memory without use of the CPU.

The DMAC initiates the data transfer with an interrupt factor speci-

fied by the DMAC channel x (x = 0, 1) hardware transfer request

source bit (DxHR), or with a software trigger.

The DxTMS [DMA Channel x (x = 0, 1) Transfer Mode Selection

Bit] selects one of two transfer modes; cycle steal mode or burst

transfer mode. In the cycle steal mode, the DMAC transfers one

byte of data for each request. In the burst transfer mode, the

DMAC transfers the number of bytes data specified by the transfer

count register for each request. The count register is a 16-bit

counter; the maximum number of data is 65,536 bytes per one re-

quest.

Figure 31 shows the DMA control block diagram and Figure 32

shows the structure of DMAC related registers.

[DMAC Index and Status Register] DMAIS

The DMAC Index and Status Register consists of various control

bits for the DMAC and its status flags.

The DMA Channel Index Bit (DCI) selects which channel ( 0 or 1)

will be accessed, since the mode registers, source registers, des-

tination registers and transfer count register of both DMAC

channels share the same SFR addresses, respectively.

[DMAC Channel x (x = 0, 1) Mode Registers 1, 2] DMAxM1,

DMAxM2

The 16 bits of DMAC Channel x Mode Registers 1 and 2 control

each operation of DMAC channels 0 and 1.

When the DMAC Channel x (x = 0, 1) Write Bit (DxDWC) is “0”,

data is simultaneously written into each latch and register of the

Source Registers, Destination Register, and Transfer Count Reg-

isters. When this bit is “1”, data is written only into their latches.

When data is read from each register, it must be read from the

higher bytes first, then the lower bytes. When writing data, write to

the lower bytes first, then the higher bytes.

Interrupt:

UART1 receive, UART1 transmit,

Serial I/O, INT0, Timer Y, CNTR1

Signal:

OBE0, IBF0 (data),

EP (endpoint) 1 receive/transmit

EP (endpoint) 2 receive/transmit

EP (endpoint) 3 receive/transmit

EP1OUT FIFO data existing

Interrupt:

UART2 receive, UART2 transmit,

INT1, Timer 1, Timer X, CNTR0

Signal:

OBE1, IBF1 (data),

EP (endpoint) 1 receive/transmit

EP (endpoint) 2 receive/transmit

EP (endpoint) 4 receive/transmit

EP1OUT FIFO data existing

Case of DMAC

channel 0

Case of DMAC

channel 1

DMAC channel X

Channel X timing

generator

Channel X transfer

source register

Channel X transfer

destination register

Channel X transfer count register

Interrupt

generator

DMACx

interrupt request

Address bus

DxCEN

DxCRR

DxUMIE

DxSWT

DxHRS3

DxHRS2

DxHRS1

DxHRS0

DxSRCE

DxSRID

DxRLD

DRLDD

DxDRCE

DxDRID

DxRLD

DRLDD

Interrupt disable flag (I flag)

Temporary register

Index status register

DxUF

DxDAUE

Mode 1

DxTMSDTSC

Mode 2

Channel X transfer

source latch

Channel X transfer

destination latch

Channel X transfer count latch

DxDWC

Data bus

DxUF

DxSFI

150

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