7641 datasheet(5/138 Pages) RENESAS

5 / 138 page

7641 Group

Rev.4.00

Aug 28, 2006

page 5 of 135

REJ03B0191-0400

Name

Function except a port function

Function

Table 2 Pin description (2)

P60/DQ0–

P67/DQ7

I/O port P5

• 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually

programmed as either input or output.

• When enabling the bus interface function, CMOS or TTL

input level can be selected as its input.

• 5-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually

programmed as either input or output.

• Master CPU bus interface pin

P70/SOF,

P71/HOLD,

P72/S1,

P73/IBF1/

HLDA,

P74/OBF1

P80/UTXD2/

SRDY,

P81/URXD2/

SCLK,

P82/CTS2/

SRXD,

P83/RTS2/

STXD,

P84/UTXD1,

P85/URXD1,

P86/CTS1,

P87/RTS1

I/O port P6

I/O port P7

I/O port P8

• 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually pro-

grammed as either input or output.

• USB function pin

• Master CPU bus interface pin

• Serial I/O pin

• UART2 pin

• UART1 pin

Remarks

•DMAOUT pin

If externally detecting the timing of DMA execution, use the signal from this pin. It is “H” level during DMA transferring. This signal is valid in the memory expansion

and microprocessor modes.

•SYNCOUT pin

If externally detecting the timing of OP code fetch, use the signal from this pin. This signal is valid in the memory expansion and microprocessor modes.

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