7641 datasheet(71/138 Pages) RENESAS

71 / 138 page

7641 Group

Rev.4.00

Aug 28, 2006

page 71 of 135

REJ03B0191-0400

(5) Low power dissipation mode

• The low power dissipation operation can be realized by stopping

the main clock XIN when using f(XCIN) as the internal system

clock. To stop the main clock, set the Main Clock (XIN-XOUT)

Stop Bit of the CPU mode register A to “1”.

• The low power dissipation operation can be realized by disabling

the reversed amplifier when inputting external clocks to the XIN

pin or XCIN pin. To disable the reversed amplifier, set the XCOUT

Oscillation Drive Disable Bit (CCR5) or XOUT Oscillation Drive

Disable Bit (CCR6) of the clock control register to “1”.

Oscillation Control

(1) Stop mode

If the STP instruction is executed, the internal clock

φ stops at “H”

level, and XIN and XCIN oscillators stop. Then the timer 1 is set to

“FF16” and the internal clock

φ divided by 8 is automatically se-

lected as its count source. Additionally, the timer 2 is set to “0116”

and the timer 1’s output is automatically selected as its count

source.

Set the Timer 1 and Timer 2 Interrupt Enable Bits to disabled (“0”)

before executing the STP instruction. When using an external in-

terrupt to release the stop mode, set the Interrupt Enable Bit to be

used to enabled (“1”) and the Interrupt Disable Flag (I) to “0”.

Oscillator restarts at reset or when an external interrupt including

USB resume interrupts is received, but the internal clock

φ re-

mains at “H” until the timer 2 underflows. The internal clock

φ is

supplied for the first time when the timer 2 underflows. Therefore

make sure not to set the Timer 1 Interrupt Request Bit and Timer

2 Interrupt Request Bit to “1” before the STP instruction stops the

oscillator.

(2) Wait mode

If the WIT instruction is executed, the internal clock

φ stops at “H”

level, but the oscillator does not stop. The internal clock

φ restarts

at reset or when an interrupt is received. Since the oscillator does

not stop, normal operation can be started immediately after the in-

ternal clock

φ is restarted.

Set the Interrupt Enable Bit to be used to release the wait mode to

enabled (“1”) and the Interrupt Disable Flag (I) to “0”.

Fig. 66 Structure of clock control register

Clock control register (address 001F16)

CCR

Reserved bits (“0” at read/write)

Fix to “0”.

XCOUT oscillation drive disable bit (CCR5)

0: XCOUT oscillation drive is enabled.

(When XCIN oscillation is enabled.)

1: XCOUT oscillation drive is disabled.

XOUT oscillation drive disable bit (CCR6)

0: XOUT oscillation drive is enabled.

(When XIN oscillation is enabled.)

1: XOUT oscillation drive is disabled.

XIN divider select bit (CCR7)

Valid when CPMA6, CPMA7 = “00”

0: f(XIN)/2 is used for the system clock.

1: f(XIN) is used for the system clock.

000 0 0

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