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7641 Datasheet(PDF) 61 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 61 Page - Renesas Technology Corp |
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61 / 138 page  7641 Group Rev.4.00 Aug 28, 2006 page 61 of 135 REJ03B0191-0400 Fig. 56 Master CPU bus interface block diagram P60/DQ0 RD WR DBB1 DBBSTS0 U7 U6 U5 U4 A00 U2 IBF0 OBF0 U7 U6 U5 U4 A01 U2 IBF1 OBF1 P61/DQ1 P62/DQ2 P63/DQ3 P64/DQ4 P65/DQ5 P66/DQ6 P67/DQ7 P72/S1 P56/R P57/W b7b6b5 b4b3 b2b1b0 RD DBBSTS1 DBB0 WR P73/IBF1 P74/OBF1 P52/OBF0 P56/R P57/W P53/IBF0 P55/A0 P54/S0 b7b6b5 b4b3b2b1b0 P55/A0 Data bus buffer control register 1 (address 004E16) Data bus buffer control register 0 (address 004A16) Output data bus buffer register 1 (address 004C16) Input data bus buffer register 1 (address 004C16) Input data bus buffer register 0 (address 004816) Output data bus buffer register 0 (address 004816) |
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