7641 datasheet(22/138 Pages) RENESAS

22 / 138 page

7641 Group

Rev.4.00

Aug 28, 2006

page 22 of 135

REJ03B0191-0400

Fig. 17 Structure of interrupt-related registers

Interrupt request register A (address 000216)

IREQA

USB function interrupt request bit

USB SOF interrupt request bit

INT0 interrupt request bit

INT1 interrupt request bit

DMAC0 interrupt request bit

DMAC1 interrupt request bit

UART1 receive buffer full interrupt request bit

UART1 transmit interrupt request bit

Interrupt polarity select register (address

001116)

IPOL

INT0 interrupt edge select bit

INT1 interrupt edge select bit

Reserved bits (“0” at read/write)

0 : Falling edge active

1 : Rising edge active

0 : Interrupts disabled

1 : Interrupts enabled

0 : No interrupt request issued

1 : Interrupt request issued

Interrupt request register B address (address 000316)

IREQB

UART1 summing error interrupt request bit

UART2 receive buffer full interrupt request bit

UART2 transmit interrupt request bit

UART2 summing error interrupt request bit

Timer X interrupt request bit

Timer Y interrupt request bit

Timer 1 interrupt request bit

Timer 2 interrupt request bit

0 : No interrupt request issued

1 : Interrupt request issued

Interrupt control register A (address 000516)

ICONA

USB function interrupt enable bit

USB SOF interrupt enable bit

INT0 interrupt enable bit

INT1 interrupt enable bit

DMAC0 interrupt enable bit

DMAC1 interrupt enable bit

UART1 receive buffer full interrupt enable bit

UART1 transmit interrupt enable bit

Interrupt request register C (address 000416)

IREQC

Timer 3 interrupt request bit

CNTR0 interrupt request bit

CNTR1 interrupt request bit

Serial I/O interrupt request bit

Input buffer full interrupt request bit

Output buffer empty interrupt request bit

Key input interrupt request bit

Reserved bit (“0” at read/write)

0 : No interrupt request issued

1 : Interrupt request issued

Interrupt control register B (address 000616)

ICONB

UART1 summing error interrupt enable bit

UART2 receive buffer full interrupt enable bit

UART2 transmit interrupt enable bit

UART2 summing error interrupt enable bit

Timer X interrupt enable bit

Timer Y interrupt enable bit

Timer 1 interrupt enable bit

Timer 2 interrupt enable bit

0 : Interrupts disabled

1 : Interrupts enabled

Interrupt control register C (address 000716)

ICONC

Timer 3 interrupt enable bit

CNTR0 interrupt enable bit

CNTR1 interrupt enable bit

Serial I/O interrupt enable bit

Input buffer full interrupt enable bit

Output buffer empty interrupt enable bit

Key input interrupt enable bit

Reserved bit (“0” at read/write)

0 : Interrupts disabled

1 : Interrupts enabled

0 0 00 00

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