7641 datasheet(75/138 Pages) RENESAS

75 / 138 page

7641 Group

Rev.4.00

Aug 28, 2006

page 75 of 135

REJ03B0191-0400

Fig. 70 Structure of CPU mode register A

CPU mode register A (address 000016)

CPMA

Processor mode bits

b1b0

0 0: Single-chip mode

0 1: Memory expansion mode

1 0: Microprocessor mode (Note 1)

1 1: Not available

Stack page select bit

0: Page 0

1: Page 1

Fix to “1”.

Sub-clock (XCIN-XCOUT) control bit

0: Stopped

1: Oscillating

Main clock (XIN-XOUT) control bit

0: Oscillating

1: Stopped

Internal system clock select bit (Note 2)

0: External clock (XIN-XOUT or XCIN-XCOUT)

1: fSYN

External clock select bit

0: XIN-XOUT

1: XCIN-XCOUT

Notes1: This is not available in the flash memory version.

2: When (CPMA 6, 7) = (0, 0), the internal system clock can be selected

between f(XIN) or f(XIN)/2 by CCR7.

The internal clock

φ is the internal system clock divided by 2.

CPU mode register B (address 000116)

CPMB

Slow memory wait select bits

b1b0

0 0: No wait

0 1: One-time wait

1 0: Two-time wait

1 1: Three-time wait

Slow memory wait mode select bits

b3b2

0 0: Software wait

0 1: Not available

1 0: RDY wait

1 1: Software wait plus RDY input anytime wait

Expanded data memory access bit

0: EDMA output disabled

1: EDMA output enabled

HOLD function enable bit

0: HOLD function disabled

1: HOLD function enabled

Resereved bit (“0” at read/write)

Fix to “1”.

1 0

Fig. 71 Structure of CPU mode register B

7641 Datasheet(PDF) 75 Page - Renesas Technology Corp

7641 Datasheet(HTML) 75 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL