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SH7201 Datasheet(PDF) 193 Page - Renesas Technology Corp

Part # SH7201
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
PDF  1196 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7201 Datasheet(HTML) 193 Page - Renesas Technology Corp

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Section 7 User Break Controller (UBC)
Rev. 2.00 Sep. 07, 2007 Page 165 of 1164
REJ09B0321-0200
7.3.2
Break Address Mask Register (BAMR)
BAMR is a 32-bit readable/writable register. BAMR specifies bits masked in the break address
bits specified by BAR. BAMR is initialized to H'00000000 by a power-on reset or in deep
standby, but retains its previous value by a manual reset or in software standby mode or sleep
mode.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0000000000000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0000000000000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16
BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0
Bit
Bit Name
Initial
Value
R/W
Description
31 to 0
BAM31 to
BAM0
All 0
R/W
Break Address Mask
Specify bits masked in the break address bits specified
by BAR (BA31 to BA0).
0: Break address bit BAn is included in the break
condition
1: Break address bit BAn is masked and not included
in the break condition
Note: n = 31 to 0



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