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SH7201 Datasheet(PDF) 190 Page - Renesas Technology Corp |
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SH7201 Datasheet(HTML) 190 Page - Renesas Technology Corp |
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190 / 1196 page  Section 7 User Break Controller (UBC) Rev. 2.00 Sep. 07, 2007 Page 162 of 1164 REJ09B0321-0200 Figure 7.1 shows a block diagram of the UBC. IDB IAB MAB FAB MDB BBR_0 BBR_1 BAR_0 BAMR_0 BDR_0 BDMR_0 BAR_1 BAMR_1 BDR_1 BDMR_1 BRCR Internaal bus (I bus) Access comparator Address comparator Channel 0 Access comparator Address comparator Data comparator Control Channel 1 User break request [Legend] BBR: BAR: BAMR: BDR: BDMR: BRCR: Break bus cycle register Break address register Break address mask register Access control Data comparator UBCTRG pin output Internal bus (I bus) CPU bus (C bus) Break data register Break data mask register Break control register Figure 7.1 Block Diagram of UBC |
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