SH7201 datasheet(195/1196 Pages) RENESAS

195 / 1196 page

Section 7 User Break Controller (UBC)

Rev. 2.00 Sep. 07, 2007 Page 167 of 1164

REJ09B0321-0200

7.3.4

Break Data Mask Register (BDMR)

BDMR is a 32-bit readable/writable register. BDMR specifies bits masked in the break data bits

specified by BDR. BDMR is initialized to H'00000000 by a power-on reset or in deep standby, but

retains its previous value by a manual reset or in software standby mode or sleep mode.

0000000000000000

R/W

0000000000000000

R/W

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24 BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16

BDM15 BDM14 BDM13 BDM12 BDM11 BDM10 BDM9 BDM8 BDM7 BDM6 BDM5 BDM4 BDM3 BDM2 BDM1 BDM0

Bit

Bit Name

Initial

Value

R/W

Description

31 to 0

BDM31 to

BDM0

All 0

R/W

Break Data Mask

Specify bits masked in the break data bits specified by

BDR (BD31 to BD0).

0: Break data bit BDn is included in the break condition

1: Break data bit BDn is masked and not included in

the break condition

Note: n = 31 to 0

Notes: 1. Set the operand size when specifying a value on a data bus as the break condition.

2. When the byte size is selected as a break condition, the same byte data must be set in

bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDMR as the break mask data. Similarly,

when the word size is selected, the same word data must be set in bits 31 to 16 and 15

to 0.

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