SH7101 datasheet(399/560 Pages) RENESAS

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Section 13 Motor Management Timer (MMT)

Rev.1.00 Sep. 18, 2008 Page 365 of 522

REJ09B0069-0100

13.3.1

Timer Mode Register (MMT_TMDR)

MMT_TMDR sets the operating mode and selects the PWM output level. (In this section, the

name of this register is abbreviated to TMDR hereafter.)

Bit

Bit Name

Initial

Value

R/W

Description

⎯

Reserved

This bit is always read as 0. The write value should

always be 0.

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

Select the clock input to MMT.

000: P

001: P

φ/4

010: P

φ/16

011: P

φ/64

100: P

φ/256

101: P

φ/1024

11x: Setting prohibited

[Legend] x: Don’t care.

OLSN

R/W

Output Level Select N

Selects the negative phase output level in the

operating modes.

0: Active level is low

1: Active level is high

OLSP

R/W

Output Level Select P

Selects the positive phase output level in the operating

modes.

0: Active level is low

1: Active level is high

MD1

MD0

R/W

Mode 3 to 0

Set the timer operating mode.

00: Operation halted

01: Operating mode 1 (Transfer at TCNT = TPDR)

10: Operating mode 2 (Transfer at TCNT = TDDR

× 2)

11: Operating mode 3 (Transfer at TCNT = TPDR or

TCNT = TDDR

× 2)

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