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HD6433644R Datasheet(PDF) 112 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 112 Page - Renesas Technology Corp |
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112 / 549 page  Section 5 Power-Down Modes Rev. 6.00 Sep 12, 2006 page 92 of 526 REJ09B0326-0600 System Control Register 2 (SYSCR2) Bit 7 6 5 4 3 2 1 0 NESEL DTON MSON SA1 SA0 Initial value 1 1 1 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W SYSCR2 is an 8-bit read/write register for power-down mode control. Upon reset, SYSCR2 is initialized to H'E0. Bits 7 to 5 Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified. Bit 4 Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency at which the watch clock signal ( φW) generated by the subclock pulse generator is sampled, in relation to the oscillator clock ( φOSC) generated by the system clock pulse generator. When φOSC = 2 to 10 MHz, clear NESEL to 0. Bit 4: NESEL Description 0 Sampling rate is φOSC/16 (initial value) 1 Sampling rate is φOSC/4 |
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