HD6433644R datasheet(116/549 Pages) RENESAS

116 / 549 page

Section 5 Power-Down Modes

Rev. 6.00 Sep 12, 2006 page 96 of 526

REJ09B0326-0600

5.3.3

Oscillator Settling Time after Standby Mode Is Cleared

Bits STS2 to STS0 in SYSCR1 should be set as follows.

• When a crystal oscillator is used

The table 5.4 gives settings for various operating frequencies. Set bits STS2 to STS0 for a

waiting time of at least 10 ms.

Table 5.4

Clock Frequency and Settling Time (times are in ms)

STS2

STS1

STS0

Waiting Time

5 MHz

4 MHz

2 MHz

1 MHz

0.5 MHz

8,192 states

1.6

2.0

4.1

8.2

16.4

16,384 states

3.2

4.1

8.2

16.4

32.8

32,768 states

6.6

8.2

16.4

32.8

65.5

65,536 states

13.1

16.4

32.8

65.5

131.1

131,072 states

26.2

32.8

65.5

131.1

262.1

Legend: * Don’t care

• When an external clock is used

Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set.

5.4

Watch Mode

5.4.1

Transition to Watch Mode

The system goes from active or subactive mode to watch mode when a SLEEP instruction is

executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.

In watch mode, operation of on-chip peripheral modules other than timer A is halted. As long as a

minimum required voltage is applied, the contents of CPU registers, the on-chip RAM and some

registers of the on-chip peripheral modules, are retained. I/O ports keep the same states as before

the transition.

HD6433644R Datasheet(PDF) 116 Page - Renesas Technology Corp

HD6433644R Datasheet(HTML) 116 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL