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HD6433644R Datasheet(PDF) 119 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 119 Page - Renesas Technology Corp |
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119 / 549 page ![]() Section 5 Power-Down Modes Rev. 6.00 Sep 12, 2006 page 99 of 526 REJ09B0326-0600 5.6.3 Operating Frequency in Subactive Mode The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are φW/2, φW/4, and φW/8. 5.7 Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ0 or IRQ1 interrupts in standby mode, timer A or IRQ0 interrupts in watch mode, or any interrupt in sleep (medium-speed) mode. A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.7.2 Clearing Active (Medium-Speed) Mode Active (medium-speed) mode is cleared by a SLEEP instruction or by input at the RES pin. • Clearing by SLEEP instruction A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 when a SLEEP instruction is executed. When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed, sleep (high-speed) mode is entered if MSON is cleared to 0 in SYSCR2, and sleep (medium- speed) mode is entered if MSON is set to 1. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See section 5.8, Direct Transfer, below for details. • Clearing by RES pin When the RES pin goes low, the CPU enters the reset state and active (medium-speed) mode is cleared. 5.7.3 Operating Frequency in Active (Medium-Speed) Mode Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1. |
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