HD6433644R datasheet(115/549 Pages) RENESAS

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Section 5 Power-Down Modes

Rev. 6.00 Sep 12, 2006 page 95 of 526

REJ09B0326-0600

• Clearing by RES input

When the

RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.

5.2.3

Clock Frequency in Sleep (Medium-Speed) Mode

Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and

MA0 bits in SYSCR1.

5.3

Standby Mode

5.3.1

Transition to Standby Mode

The system goes from active mode to standby mode when a SLEEP instruction is executed while

the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in

TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip

peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of

CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip

RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O

ports go to the high-impedance state.

5.3.2

Clearing Standby Mode

Standby mode is cleared by an interrupt (IRQ1 or IRQ0) or by input at the RES pin.

• Clearing by interrupt

When an interrupt is requested, the system clock pulse generator starts. After the time set in

bits STS2–STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire

chip, standby mode is cleared, and interrupt exception handling starts. Operation resumes in

active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON

= 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is

disabled in the interrupt enable register.

• Clearing by RES input

When the

RES pin goes low, the system clock pulse generator starts. After the pulse generator

output has stabilized, if the

RES pin is driven high, the CPU starts reset exception handling.

Since system clock signals are supplied to the entire chip as soon as the system clock pulse

generator starts functioning, the

RES pin should be kept at the low level until the pulse

generator output stabilizes.

HD6433644R Datasheet(PDF) 115 Page - Renesas Technology Corp