HD6433644R datasheet(154/549 Pages) RENESAS

154 / 549 page

Section 6 ROM

Rev. 6.00 Sep 12, 2006 page 134 of 526

REJ09B0326-0600

Prewrite Flowchart

Start

End of prewrite

Programming error

Set erase block register

(set bit for block to be programmed to 1)

Select program mode

(P bit = 1 in FLMCR)

Set start address *6

n = 1

Wait (x)

µs *4

Clear P bit

End of programming

Yes

Enable watchdog timer *2

Disable watchdog timer

Wait (tvs1) µs *5

n + 1

→ n

Address + 1

→ address

Double the programming time

× 2 → x)

Clear erase block register

(clear bit for programmed block to 0)

Write H'00 to flash memory

(flash memory latches programmed address

and data) *1

Prewrite verify *3

(read data H'00?)

≥ N? *5

Last address?

Notes: 1. Write using a byte transfer instruction.

2. For the timer overflow interval, set the

timer counter value (TCW) to H'FE.

3. In prewrite-verify mode, P, E, PV, and EV

are all cleared to 0, and 12 V is applied to

the VPP pin. Read using a byte transfer

4. Programming time x is successively

incremented to initial set value

× 2n–1

(n = 1 to 6). The initial value should

therefore be set to 15.8

µs or less to make

the total programming time 1 ms or less.

5. tvs1: 4 µs or more

6 (set N so that the total programming

time does not exceed 1 ms)

6. The start address and last address are the

start address and last address of the block

to be erased.

Figure 6.15 Prewrite Flowchart

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