HD6433644R datasheet(153/549 Pages) RENESAS

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Section 6 ROM

Rev. 6.00 Sep 12, 2006 page 133 of 526

REJ09B0326-0600

6.7.6

Erase Flowcharts and Sample Programs

Flowchart for Erasing One Block

Start

End of erase

Erase error

Set erase block register

(set bit for block to be erased to 1)

Write 0 data in all addresses to be erased

(prewrite)*1

Select erase mode

(E bit = 1 in FLMCR)

n = 1

Wait (x) ms *5

Clear E bit

Erasing halts

End of erase-verify

Yes

Enable watchdog timer *2

Disable watchdog timer

Select erase-verify mode

(EV bit = 1)

Dummy write to verify address *3

(flash memory latches

address)

Set block start address as

verify address

Wait (tvs1) µs *6

Wait (tvs2) µs *6

Clear EV bit

Address + 1

→ address

Clear EV bit

n + 1

→ n

Double the erase time

× 2 → x)

Clear erase block register

(clear bit for erased block to 0)

Verify *4

(read data H'FF?)

Last address?

≥ N? *6

> 4?

Notes: 1. Program all addresses to be erased by

following the prewrite flowchart.

2. Set the watchdog timer overflow interval to

the initial value shown in table 6.12.

3. For the erase-verify dummy write, write H'FF

using a byte transfer instruction.

4. For the erase-verify operation, read the data

using a byte transfer instruction. When

erasing multiple blocks, clear the erase block

additional erasing only for unerased blocks.

5. Erase time x is successively incremented to

initial set value x 2n-1 (n = 1 to 4), and is

fixed from the 4th time onward. An initial

value of 6.25 ms or less should be set, and

the time for one erasure should be 50 ms or

less.

6. tvs1: 4 µs or more

tvs2: 2 µs or more

602 (set N so that the total erase time

does not exceed 30 s)

Figure 6.14 Erase Flowchart

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