HD6433644R datasheet(149/549 Pages) RENESAS

149 / 549 page

Section 6 ROM

Rev. 6.00 Sep 12, 2006 page 129 of 526

REJ09B0326-0600

6.7.3

Programming Flowchart and Sample Program

Flowchart for Programming One Byte

Start

End (1-byte data programmed)

Programming error

Set erase block register

(set bit for block to be programmed to 1)

Select program mode

(P bit = 1 in FLMCR)

n = 1

Wait (x)

µs *4

Clear P bit

End of programming

End of verify

Yes

Enable watchdog timer *2

Disable watchdog timer

Select program-verify mode

(PV bit = 1 in FLMCR)

Wait (tvs1)

µs *5

Clear PV bit

n + 1

→ n

Double the programming time

× 2 → x)

Clear erase block register

(clear bit for programmed block to 0)

Write data to flash memory

(flash memory latches write address

and data) *1

Verify *3

(read memory)

≥ N? *5

Notes: 1. Write the data to be programmed using a byte

transfer instruction.

2. For the timer overflow interval, set the timer

counter value (TCW) to H'FE.

3. Read the memory data to be verified using a

byte transfer instruction.

4. Programming time x is successively

incremented to initial set value

× 2n–1 (n = 1 to

6). The initial value should therefore be set to

15.8

µs or less to make the total

programming time 1 ms or less.

5. tvs1: 4 µs or more

6 (set N so that total programming time

does not exceed 1 ms)

Figure 6.13 Programming Flowchart

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